![]() Smash : mixed signal (spice), Verilog, VHDL simulator.Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.You can even use it to replace your existing Modelsim/VCS/NCverilog licenses. I could not verify the SV testbench support, other than that everything else looks same as Modelsim. ![]()
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